Intelligent slice caching

ABSTRACT

Systems and methods for intelligent slice caching in a dispersed storage network. The methods include determining a minimum slice access rate for encoded data slices to be stored, determining a least access rate of a least accessed encoded data slice stored, determining an estimated access rate for an encoded data slice and determining whether to store the encoded data slice in small fast memory as a cached encoded data slice based on the minimum slice access rate, the least access rate, and the estimated access rate. The method further includes facilitating storage of the encoded data slice in small fast memory. The method may also include updating the minimum slice access rate and transferring an encoded data slice stored in small fast memory to large slow memory when an actual access rate is less than the minimum slice access rate or is less than the least access rate.

CROSS REFERENCE TO RELATED APPLICATIONS

The present U.S. Utility Patent Application claims priority pursuant to35 U.S.C. §119(e) to U.S. Provisional Application No. 62/272,848 filed30 Dec. 2015, entitled “OPTIMIZING UTILIZATION OF STORAGE MEMORY IN ADISPERSED STORAGE NETWORK,” which is hereby incorporated herein byreference in its entirety and made part of the present U.S. UtilityPatent Application for all purposes.

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

Not Applicable.

INCORPORATION-BY-REFERENCE OF MATERIAL SUBMITTED ON A COMPACT DISC

Not Applicable.

BACKGROUND OF THE INVENTION

Technical Field of the Invention

This invention relates generally to computer networks, and moreparticularly to dispersed or cloud storage.

Description of Related Art

Computing devices are known to communicate data, process data, and/orstore data. Such computing devices range from wireless smart phones,laptops, tablets, personal computers (PC), work stations, and video gamedevices, to data centers that support millions of web searches, stocktrades, or on-line purchases every day. In general, a computing deviceincludes a central processing unit (CPU), a memory system, userinput/output interfaces, peripheral device interfaces, and aninterconnecting bus structure.

As is further known, a computer may effectively extend its CPU by using“cloud computing” to perform one or more computing functions (e.g., aservice, an application, an algorithm, an arithmetic logic function,etc.) on behalf of the computer. Further, for large services,applications, and/or functions, cloud computing may be performed bymultiple cloud computing resources in a distributed manner to improvethe response time for completion of the service, application, and/orfunction. For example, Hadoop is an open source software framework thatsupports distributed applications enabling application execution bythousands of computers.

In addition to cloud computing, a computer may use “cloud storage” aspart of its memory system. As is known, cloud storage enables a user,via its computer, to store files, applications, etc. on a remote orInternet storage system. The remote or Internet storage system mayinclude a RAID (redundant array of independent disks) system and/or adispersed storage system that uses an error correction scheme to encodedata for storage.

In a RAID system, a RAID controller adds parity data to the originaldata before storing it across an array of disks. The parity data iscalculated from the original data such that the failure of a single disktypically will not result in the loss of the original data. While RAIDsystems can address certain memory device failures, these systems maysuffer from effectiveness, efficiency and security issues. For instance,as more disks are added to the array, the probability of a disk failurerises, which may increase maintenance costs. When a disk fails, forexample, it needs to be manually replaced before another disk(s) failsand the data stored in the RAID system is lost. To reduce the risk ofdata loss, data on a RAID device is often copied to one or more otherRAID devices. While this may reduce the possibility of data loss, italso raises security issues since multiple copies of data may beavailable, thereby increasing the chances of unauthorized access. Inaddition, co-location of some RAID devices may result in a risk of acomplete data loss in the event of a natural disaster, fire, powersurge/outage, etc.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING(S)

FIG. 1 is a schematic block diagram of an embodiment of a dispersed, ordistributed, storage network (DSN) in accordance with the presentdisclosure;

FIG. 2 is a schematic block diagram of an embodiment of a computing corein accordance with the present disclosure;

FIG. 3 is a schematic block diagram of an example of dispersed storageerror encoding of data in accordance with the present disclosure;

FIG. 4 is a schematic block diagram of a generic example of an errorencoding function in accordance with the present disclosure;

FIG. 5 is a schematic block diagram of a specific example of an errorencoding function in accordance with the present disclosure;

FIG. 6 is a schematic block diagram of an example of slice naminginformation for an encoded data slice (EDS) in accordance with thepresent disclosure;

FIG. 7 is a schematic block diagram of an example of dispersed storageerror decoding of data in accordance with the present disclosure;

FIG. 8 is a schematic block diagram of a generic example of an errordecoding function in accordance with the present disclosure;

FIG. 9 is a schematic block diagram of an example of a dispersed storagenetwork in accordance with the present disclosure;

FIG. 10A is a schematic block diagram of another embodiment of adispersed storage network (DSN) in accordance with the presentinvention; and

FIG. 10B is a flowchart illustrating an example of intelligent slicecaching in a dispersed storage network (DSN).

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 is a schematic block diagram of an embodiment of a dispersed, ordistributed, storage network (DSN) 10 that includes a plurality ofdispersed storage (DS) computing devices or processing units 12-16, a DSmanaging unit 18, a DS integrity processing unit 20, and a DSN memory22. The components of the DSN 10 are coupled to a network 24, which mayinclude one or more wireless and/or wire lined communication systems;one or more non-public intranet systems and/or public internet systems;and/or one or more local area networks (LAN) and/or wide area networks(WAN).

The DSN memory 22 includes a plurality of dispersed storage units 36 (DSunits) that may be located at geographically different sites (e.g., onein Chicago, one in Milwaukee, etc.), at a common site, or a combinationthereof. For example, if the DSN memory 22 includes eight dispersedstorage units 36, each storage unit is located at a different site. Asanother example, if the DSN memory 22 includes eight storage units 36,all eight storage units are located at the same site. As yet anotherexample, if the DSN memory 22 includes eight storage units 36, a firstpair of storage units are at a first common site, a second pair ofstorage units are at a second common site, a third pair of storage unitsare at a third common site, and a fourth pair of storage units are at afourth common site. Note that a DSN memory 22 may include more or lessthan eight storage units 36.

DS computing devices 12-16, the managing unit 18, and the integrityprocessing unit 20 include a computing core 26, and network orcommunications interfaces 30-33 which can be part of or external tocomputing core 26. DS computing devices 12-16 may each be a portablecomputing device and/or a fixed computing device. A portable computingdevice may be a social networking device, a gaming device, a cell phone,a smart phone, a digital assistant, a digital music player, a digitalvideo player, a laptop computer, a handheld computer, a tablet, a videogame controller, and/or any other portable device that includes acomputing core. A fixed computing device may be a computer (PC), acomputer server, a cable set-top box, a satellite receiver, a televisionset, a printer, a fax machine, home entertainment equipment, a videogame console, and/or any type of home or office computing equipment.Note that each of the managing unit 18 and the integrity processing unit20 may be separate computing devices, may be a common computing device,and/or may be integrated into one or more of the computing devices 12-16and/or into one or more of the dispersed storage units 36.

Each interface 30, 32, and 33 includes software and/or hardware tosupport one or more communication links via the network 24 indirectlyand/or directly. For example, interface 30 supports a communication link(e.g., wired, wireless, direct, via a LAN, via the network 24, etc.)between computing devices 14 and 16. As another example, interface 32supports communication links (e.g., a wired connection, a wirelessconnection, a LAN connection, and/or any other type of connectionto/from the network 24) between computing devices 12 and 16 and the DSNmemory 22. As yet another example, interface 33 supports a communicationlink for each of the managing unit 18 and the integrity processing unit20 to the network 24.

In general, and with respect to DS error encoded data storage andretrieval, the DSN 10 supports three primary operations: storagemanagement, data storage and retrieval. More specifically computingdevices 12 and 16 include a dispersed storage (DS) client module 34,which enables the computing device to dispersed storage error encode anddecode data (e.g., data object 40) as subsequently described withreference to one or more of FIGS. 3-8. In this example embodiment,computing device 16 functions as a dispersed storage processing agentfor computing device 14. In this role, computing device 16 dispersedstorage error encodes and decodes data on behalf of computing device 14.With the use of dispersed storage error encoding and decoding, the DSN10 is tolerant of a significant number of storage unit failures (thenumber of failures is based on parameters of the dispersed storage errorencoding function) without loss of data and without the need for aredundant or backup copies of the data. Further, the DSN 10 stores datafor an indefinite period of time without data loss and in a securemanner (e.g., the system is very resistant to unauthorized attempts ataccessing or hacking the data).

The second primary function (i.e., distributed data storage andretrieval) begins and ends with a DS computing devices 12-14. Forinstance, if a second type of computing device 14 has data 40 to storein the DSN memory 22, it sends the data 40 to the DS computing device 16via its interface 30. The interface 30 functions to mimic a conventionaloperating system (OS) file system interface (e.g., network file system(NFS), flash file system (FFS), disk file system (DFS), file transferprotocol (FTP), web-based distributed authoring and versioning (WebDAV),etc.) and/or a block memory interface (e.g., small computer systeminterface (SCSI), internet small computer system interface (iSCSI),etc.).

In operation, the managing unit 18 performs DS management services. Forexample, the managing unit 18 establishes distributed data storageparameters (e.g., vault creation, distributed storage parameters,security parameters, billing information, user profile information,etc.) for computing devices 12-16 individually or as part of a group ofuser devices. As a specific example, the managing unit 18 coordinatescreation of a vault (e.g., a virtual memory block associated with aportion of an overall namespace of the DSN) within the DSN memory 22 fora user device, a group of devices, or for public access and establishesper vault dispersed storage (DS) error encoding parameters for a vault.The managing unit 18 facilitates storage of DS error encoding parametersfor each vault by updating registry information of the DSN 10, where theregistry information may be stored in the DSN memory 22, a computingdevice 12-16, the managing unit 18, and/or the integrity processing unit20.

The DS error encoding parameters (e.g., or dispersed storage errorcoding parameters) include data segmenting information (e.g., how manysegments data (e.g., a file, a group of files, a data block, etc.) isdivided into), segment security information (e.g., per segmentencryption, compression, integrity checksum, etc.), error codinginformation (e.g., pillar width, decode threshold, read threshold, writethreshold, etc.), slicing information (e.g., the number of encoded dataslices that will be created for each data segment); and slice securityinformation (e.g., per encoded data slice encryption, compression,integrity checksum, etc.).

The managing unit 18 creates and stores user profile information (e.g.,an access control list (ACL)) in local memory and/or within memory ofthe DSN memory 22. The user profile information includes authenticationinformation, permissions, and/or the security parameters. The securityparameters may include encryption/decryption scheme, one or moreencryption keys, key generation scheme, and/or data encoding/decodingscheme.

The managing unit 18 creates billing information for a particular user,a user group, a vault access, public vault access, etc. For instance,the managing unit 18 tracks the number of times a user accesses anon-public vault and/or public vaults, which can be used to generateper-access billing information. In another instance, the managing unit18 tracks the amount of data stored and/or retrieved by a user deviceand/or a user group, which can be used to generate per-data-amountbilling information. As will be described in more detail in conjunctionwith FIGS. 10A and 10B, usage can be determined by a managing unit 18 ona byte-hour basis.

As another example, the managing unit 18 performs network operations,network administration, and/or network maintenance. Network operationsincludes authenticating user data allocation requests (e.g., read and/orwrite requests), managing creation of vaults, establishingauthentication credentials for user devices, adding/deleting components(e.g., user devices, storage units, and/or computing devices with a DSclient module 34) to/from the DSN 10, and/or establishing authenticationcredentials for the storage units 36. Network operations can furtherinclude monitoring read, write and/or delete communications attempts,which attempts could be in the form of requests. Network administrationincludes monitoring devices and/or units for failures, maintaining vaultinformation, determining device and/or unit activation status,determining device and/or unit loading, and/or determining any othersystem level operation that affects the performance level of the DSN 10.Network maintenance includes facilitating replacing, upgrading,repairing, and/or expanding a device and/or unit of the DSN 10.

To support data storage integrity verification within the DSN 10, theintegrity processing unit 20 (and/or other devices in the DSN 10 such asmanaging unit 18) may assess and perform rebuilding of ‘bad’ or missingencoded data slices. At a high level, the integrity processing unit 20performs rebuilding by periodically attempting to retrieve/list encodeddata slices, and/or slice names of the encoded data slices, from the DSNmemory 22. Retrieved encoded slices are assessed and checked for errorsdue to data corruption, outdated versioning, etc. If a slice includes anerror, it is flagged as a ‘bad’ or ‘corrupt’ slice. Encoded data slicesthat are not received and/or not listed may be flagged as missingslices. Bad and/or missing slices may be subsequently rebuilt usingother retrieved encoded data slices that are deemed to be good slices inorder to produce rebuilt slices. A multi-stage decoding process may beemployed in certain circumstances to recover data even when the numberof valid encoded data slices of a set of encoded data slices is lessthan a relevant decode threshold number. The rebuilt slices may then bewritten to DSN memory 22. Note that the integrity processing unit 20 maybe a separate unit as shown, included in DSN memory 22, included in thecomputing device 16, managing unit 18, stored on a DS unit 36, and/ordistributed among multiple storage units 36.

FIG. 2 is a schematic block diagram of an embodiment of a computing core26 that includes a processing module 50, a memory controller 52, mainmemory 54, a video graphics processing unit 55, an input/output (IO)controller 56, a peripheral component interconnect (PCI) interface 58,an IO interface module 60, at least one IO device interface module 62, aread only memory (ROM) basic input output system (BIOS) 64, and one ormore memory interface modules. The one or more memory interfacemodule(s) includes one or more of a universal serial bus (USB) interfacemodule 66, a host bus adapter (HBA) interface module 68, a networkinterface module 70, a flash interface module 72, a hard drive interfacemodule 74, and a DSN interface module 76.

The DSN interface module 76 functions to mimic a conventional operatingsystem (OS) file system interface (e.g., network file system (NFS),flash file system (FFS), disk file system (DFS), file transfer protocol(FTP), web-based distributed authoring and versioning (WebDAV), etc.)and/or a block memory interface (e.g., small computer system interface(SCSI), internet small computer system interface (iSCSI), etc.). The DSNinterface module 76 and/or the network interface module 70 may functionas one or more of the interface 30-33 of FIG. 1. Note that the IO deviceinterface module 62 and/or the memory interface modules 66-76 may becollectively or individually referred to as IO ports.

FIG. 3 is a schematic block diagram of an example of dispersed storageerror encoding of data. When a computing device 12 or 16 has data tostore it disperse storage error encodes the data in accordance with adispersed storage error encoding process based on dispersed storageerror encoding parameters. The dispersed storage error encodingparameters include an encoding function (e.g., information dispersalalgorithm, Reed-Solomon, Cauchy Reed-Solomon, systematic encoding,non-systematic encoding, on-line codes, etc.), a data segmentingprotocol (e.g., data segment size, fixed, variable, etc.), and per datasegment encoding values. The per data segment encoding values include atotal, or pillar width, number (T) of encoded data slices per encodingof a data segment (i.e., in a set of encoded data slices); a decodethreshold number (D) of encoded data slices of a set of encoded dataslices that are needed to recover the data segment; a read thresholdnumber (R) of encoded data slices to indicate a number of encoded dataslices per set to be read from storage for decoding of the data segment;and/or a write threshold number (W) to indicate a number of encoded dataslices per set that must be accurately stored before the encoded datasegment is deemed to have been properly stored. The dispersed storageerror encoding parameters may further include slicing information (e.g.,the number of encoded data slices that will be created for each datasegment) and/or slice security information (e.g., per encoded data sliceencryption, compression, integrity checksum, etc.).

In the present example, Cauchy Reed-Solomon has been selected as theencoding function (a generic example is shown in FIG. 4 and a specificexample is shown in FIG. 5); the data segmenting protocol is to dividethe data object into fixed sized data segments; and the per data segmentencoding values include: a pillar width of 5, a decode threshold of 3, aread threshold of 4, and a write threshold of 4. In accordance with thedata segmenting protocol, the computing device 12 or 16 divides the data(e.g., a file (e.g., text, video, audio, etc.), a data object, or otherdata arrangement) into a plurality of fixed sized data segments (e.g., 1through Y of a fixed size in range of Kilo-bytes to Tera-bytes or more).The number of data segments created is dependent of the size of the dataand the data segmenting protocol.

The computing device 12 or 16 then disperse storage error encodes a datasegment using the selected encoding function (e.g., Cauchy Reed-Solomon)to produce a set of encoded data slices. FIG. 4 illustrates a genericCauchy Reed-Solomon encoding function, which includes an encoding matrix(EM), a data matrix (DM), and a coded matrix (CM). The size of theencoding matrix (EM) is dependent on the pillar width number (T) and thedecode threshold number (D) of selected per data segment encodingvalues. To produce the data matrix (DM), the data segment is dividedinto a plurality of data blocks and the data blocks are arranged into Dnumber of rows with Z data blocks per row. Note that Z is a function ofthe number of data blocks created from the data segment and the decodethreshold number (D). The coded matrix is produced by matrix multiplyingthe data matrix by the encoding matrix.

FIG. 5 illustrates a specific example of Cauchy Reed-Solomon encodingwith a pillar number (T) of five and decode threshold number of three.In this example, a first data segment is divided into twelve data blocks(D1-D12). The coded matrix includes five rows of coded data blocks,where the first row of X11-X14 corresponds to a first encoded data slice(EDS 1_1), the second row of X21-X24 corresponds to a second encodeddata slice (EDS 2_1), the third row of X31-X34 corresponds to a thirdencoded data slice (EDS 3_1), the fourth row of X41-X44 corresponds to afourth encoded data slice (EDS 4_1), and the fifth row of X51-X54corresponds to a fifth encoded data slice (EDS 5_1). Note that thesecond number of the EDS designation corresponds to the data segmentnumber. In the illustrated example, the value X11=aD1+bD5+cD9,X12=aD2+bD6+cD10, . . . X53=mD3+nD7+oD11, and X54=mD4+nD8+oD12.

Returning to the discussion of FIG. 3, the computing device also createsa slice name (SN) for each encoded data slice (EDS) in the set ofencoded data slices. A typical format for a slice name 80 is shown inFIG. 6. As shown, the slice name (SN) 80 includes a pillar number of theencoded data slice (e.g., one of 1-T), a data segment number (e.g., oneof 1-Y), a vault identifier (ID), a data object identifier (ID), and mayfurther include revision level information of the encoded data slices.The slice name functions as at least part of a DSN address for theencoded data slice for storage and retrieval from the DSN memory 22.

As a result of encoding, the computing device 12 or 16 produces aplurality of sets of encoded data slices, which are provided with theirrespective slice names to the storage units for storage. As shown, thefirst set of encoded data slices includes EDS 1_1 through EDS 5_1 andthe first set of slice names includes SN 1_1 through SN 5_1 and the lastset of encoded data slices includes EDS 1_Y through EDS 5_Y and the lastset of slice names includes SN 1_Y through SN 5_Y.

FIG. 7 is a schematic block diagram of an example of dispersed storageerror decoding of a data object that was dispersed storage error encodedand stored in the example of FIG. 4. In this example, the computingdevice 12 or 16 retrieves from the storage units at least the decodethreshold number of encoded data slices per data segment. As a specificexample, the computing device retrieves a read threshold number ofencoded data slices.

In order to recover a data segment from a decode threshold number ofencoded data slices, the computing device uses a decoding function asshown in FIG. 8. As shown, the decoding function is essentially aninverse of the encoding function of FIG. 4. The coded matrix includes adecode threshold number of rows (e.g., three in this example) and thedecoding matrix in an inversion of the encoding matrix that includes thecorresponding rows of the coded matrix. For example, if the coded matrixincludes rows 1, 2, and 4, the encoding matrix is reduced to rows 1, 2,and 4, and then inverted to produce the decoding matrix.

FIG. 9 is a diagram of an example of a dispersed storage network. Thedispersed storage network includes a DS (dispersed storage) clientmodule 34 (which may be in DS computing devices 12 and/or 16 of FIG. 1),a network 24, and a plurality of DS units 36-1 . . . 36-n (which may bestorage units 36 of FIG. 1 and which form at least a portion of DSmemory 22 of FIG. 1), a DSN managing unit 18, and a DS integrityverification module (not shown). The DS client module 34 includes anoutbound DS processing section 81 and an inbound DS processing section82. Each of the DS units 36-1 . . . 36-n includes a controller 86, aprocessing module 84 (e.g. computer processor) including acommunications interface for communicating over network 24 (not shown),memory 88, a DT (distributed task) execution module 90, and a DS clientmodule 34.

In an example of operation, the DS client module 34 receives data 92.The data 92 may be of any size and of any content, where, due to thesize (e.g., greater than a few Terabytes), the content (e.g., securedata, etc.), and/or concerns over security and loss of data, distributedstorage of the data is desired. For example, the data 92 may be one ormore digital books, a copy of a company's emails, a large-scale Internetsearch, a video security file, one or more entertainment video files(e.g., television programs, movies, etc.), data files, and/or any otherlarge amount of data (e.g., greater than a few Terabytes).

Within the DS client module 34, the outbound DS processing section 81receives the data 92. The outbound DS processing section 81 processesthe data 92 to produce slice groupings 96. As an example of suchprocessing, the outbound DS processing section 81 partitions the data 92into a plurality of data partitions. For each data partition, theoutbound DS processing section 81 dispersed storage (DS) error encodesthe data partition to produce encoded data slices and groups the encodeddata slices into a slice grouping 96.

The outbound DS processing section 81 then sends, via the network 24,the slice groupings 96 to the DS units 36-1 . . . 36-n of the DSN memory22 of FIG. 1. For example, the outbound DS processing section 81 sendsslice group 1 to DS storage unit 36-1. As another example, the outboundDS processing section 81 sends slice group #n to DS unit #n.

In one example of operation, the DS client module 34 requests retrievalof stored data within the memory of the DS units 36. In this example,the task 94 is retrieve data stored in the DSN memory 22. Accordingly,and according to one embodiment, the outbound DS processing section 81converts the task 94 into a plurality of partial tasks 98 and sends thepartial tasks 98 to the respective DS storage units 36-1 . . . 36-n.

In response to the partial task 98 of retrieving stored data, a DSstorage unit 36 identifies the corresponding encoded data slices 99 andretrieves them. For example, DS unit #1 receives partial task #1 andretrieves, in response thereto, retrieved slices #1. The DS units 36send their respective retrieved slices 99 to the inbound DS processingsection 82 via the network 24.

The inbound DS processing section 82 converts the retrieved slices 99into data 92. For example, the inbound DS processing section 82de-groups the retrieved slices 99 to produce encoded slices per datapartition. The inbound DS processing section 82 then DS error decodesthe encoded slices per data partition to produce data partitions. Theinbound DS processing section 82 de-partitions the data partitions torecapture the data 92.

In one example of operation, the DSN of FIG. 1 is used to performintelligent slice caching. Explanations of this process are set outbelow in conjunction with FIGS. 10A and 10B. While described in thecontext of functionality provided by DS units 36, this functionality maybe implemented utilizing any module and/or unit of a dispersed storagenetwork (DSN) including the DS Processing Unit 16, the DS Managing Unit18 and/or the Integrity Processing Unit 20, shown in FIG. 1.

In a DS unit, with a relatively, smaller high speed memory and arelatively larger low speed memory, moving more frequently accessedobjects to the high speed memory can increase performance and reducelatency. However, for some forms of memory, frequent writes can causedegradation and wear. Therefore, in a DS unit utilizing such ahighspeed, but wear-sensitive form of memory, more intelligent decisionmaking may be utilized to optimally “cache” items in the high speedmemory so as to reduce wear and keep it within an acceptable boundary.The effectiveness of a placement of a slice in the high speed memory ofa DS unit can, in one example, be measured in terms of the number oftimes it is accessed per time frame or period that slice is moved intothe high speed memory, and before it is replaced with something else.One mechanism to achieve these goals is to set a minimum bar which aslice's access rate must exceed before it can be moved into the highspeed memory. This bar can be raised or lowered, such that entry to, andeviction from, the high speed memory's cache can be lowered or increasedto stay within the limits of the high speed, but wear-sensitive memorydevice. Once the bar is set, a slice's access patterns may be measuredaccording to: Frequency of access for the slice; and the Length of timethe slice last remained in the cache. According to one example, when aslice's access frequency exceeds that of the least frequently accessedslice in the cache, and the rate exceeds the minimum bar for moving anitem into the cache, then the slice is moved to the high speed memorysuch that future access requests can be satisfied from that memory.

In another example, this same logic described above can be applied in aDS processing unit 16, only for the ds processing unit 16 it is appliedto restored objects, rather than encoded data slices. Also, when loadbalancers/requesters know that a DS processing unit is using such acaching logic, it may purposely direct repeated requests for that sameobject to the same DS processing unit to maximize use of its cache, andlikewise a DS processing unit requesting slices from a DS unit can dothe same (by reusing the same threshold DS units for reading thoseslices when the slices are repeatedly requested).

FIG. 10A is a schematic block diagram of another embodiment of adispersed storage network that includes a set of storage units 36-1,36-2 . . . 36-n, the network 24 of FIG. 1, and the distributed storage(DS) processing unit 16 of FIG. 1. Each storage unit includes arespective computer processor or processing module 84 of FIG. 9 (84-1,84-2 . . . 84-n), a small fast memory (88-1-1, 88-2-1 . . . 88-n−1), anda large slow memory (88-1-2, 88-2-2 . . . 88-n−2). According to thisexample the large slow memory has more memory capacity than the smallfast memory and the small fast memory has a faster access latency timesthan the large slow memory. Each of the small fast memory and the largeslow memory may be implemented utilizing the memory 88 of FIG. 9. Forexample, the small fast memory is implemented utilizing solid statememory technology and the large slow memory is implemented utilizingmagnetic disk drive technology. Each storage unit may be implementedutilizing the DS execution unit 36 of FIG. 1. According to one example,the DSN functions to optimize utilization of storage memory.

In an example of operation of the optimizing of utilization of thestorage memory, the processing modules 84-1, 84-2 . . . 84-n (as thecase may be) determine a minimum slice access rate for slices (500-1,500-2 and 500-n) to be stored in the respective small fast memory88-1-1, 88-2-1 . . . 88-n−1. The determining may be based on one or moreof a historical access rate, an estimated access rate for one or moreencoded data slices, a memory wear factor (i.e., maximum number of writeper unit of time), and a capacity level of the small fast memory. Havingdetermined the minimum slice access rate, the respective processingmodule 84-1, 84-2 . . . 84-n determines a respective least access rateof a least accessed encoded data slice stored in the respective smallfast memory. For example, the respective processing module 84-1, 84-2 .. . 84-n measures access rates of encoded data slices stored within thesmall fast memory and identifies a minimum access rate as the leastaccess rate.

Having determined the least access rate, the respective processingmodule 84-1, 84-2 . . . 84-n determines an estimated access rate for anencoded data slice. The determining includes at least one of identifyingthe slice identifying within a memory of an associated storage unit,measuring an actual access rate, and receiving the estimated accessrate. For example, the processing module 84-1 of the storage unit 1receives a write slice request that includes an encoded data slice 500-1of a set of encoded data slices for storage 500-1, 500-2 . . . 500-n andan estimated access rate for the encoded data slice 500-1, where the DSprocessing unit 16 generates the set of encoded data slices, and sends,via the network 24, the set of encoded data slices to the set of storageunits.

Having determined the estimated access rate for the encoded data slice,the respective processing module 84-1, 84-2 . . . 84-n determineswhether to store (e.g., new to store, maintain storage) respectiveencoded data slice 500-1, 500-2 . . . 500-n in the respective small fastmemory 88-1-1, 88-2-1 . . . 88-n−1 as a cached encoded data slice basedon the minimum slice access rate, the least access rate, and theestimated access rate. For example, the processing module 84-1 indicatesto store the encoded data slice 500-1 in the small fast memory 88-1-1 ofstorage unit 36-1 when the estimated access rate is greater than theminimum slice access rate and is greater than the least access rate.

When determining to store a respective encoded data slice in arespective small fast memory 88-1-1, 88-2-1 . . . 88-n−1, the respectiveprocessing module 84-1, 84-2 . . . 84-n facilitates storage of therespective encoded data slice 500-1, 500-2 . . . 500-n of a small fastmemory. The facilitating includes one of the processing module 84storing a received encoded data slice of a small fast memory andtransferring the encoded data slice from the large slow memory to thesmall fast memory.

FIG. 10B is a flowchart illustrating an example of optimizingutilization of storage memory. The method includes a step 600 where aprocessing module (e.g., of a storage unit) determines a minimum sliceaccess rate for encoded data slices to be stored in a small fast memory.The determining may be based on one or more of historical access rates,a memory wear factor, and a capacity level of the small fast memory. Themethod continues at a step 602 where the processing module determines aleast access rate of a least accessed encoded data slice stored in thesmall fast memory. The determining includes one or more of measuringaccess rates of encoded data slices stored within the small fast memoryand identifying a minimum access rate as the least access rate.

The method continues at the step 604 where the processing moduledetermines an estimated access rate for an encoded data slice. Thedetermining includes one or more of identifying the encoded data slice(i.e., receiving, identifying within a memory the storage unit),measuring an actual access rate, and receiving the estimated accessrate. The method continues at the step 606 where the processing moduledetermines whether to store the encoded data slice in the small fastmemory as a cached encoded data slice based on the minimum slice accessrate, the least access rate, and the estimated access rate. According toone example, step 606 results in producing a determination. For example,the processing module indicates to store the encoded data slice in thesmall fast memory when the estimated access rate is greater than theminimum slice access rate and is greater than the least access rate.

When storing the encoded data slice of a small fast memory, the methodcontinues at the step 608 where the processing module facilitatesstorage of the encoded data slice in the small fast memory. Thefacilitating includes one of storing the received encoded data slice inthe small fast memory and transferring the encoded data slice from alarge slow memory to the small fast memory. Alternatively, or inaddition to, the processing module updates the minimum slice access rateand transfers and encoded data slice stored in small fast memory to thelarge slow memory when an actual access rate is less than the minimumslice access rate or is less than the least access rate.

As may be used herein, the terms “substantially” and “approximately”provides an industry-accepted tolerance for its corresponding termand/or relativity between items. Such an industry-accepted toleranceranges from less than one percent to fifty percent and corresponds to,but is not limited to, component values, integrated circuit processvariations, temperature variations, rise and fall times, and/or thermalnoise. Such relativity between items ranges from a difference of a fewpercent to magnitude differences. As may also be used herein, theterm(s) “configured to”, “operably coupled to”, “coupled to”, and/or“coupling” includes direct coupling between items and/or indirectcoupling between items via an intervening item (e.g., an item includes,but is not limited to, a component, an element, a circuit, and/or amodule) where, for an example of indirect coupling, the intervening itemdoes not modify the information of a signal but may adjust its currentlevel, voltage level, and/or power level. As may further be used herein,inferred coupling (i.e., where one element is coupled to another elementby inference) includes direct and indirect coupling between two items inthe same manner as “coupled to”. As may even further be used herein, theterm “configured to”, “operable to”, “coupled to”, or “operably coupledto” indicates that an item includes one or more of power connections,input(s), output(s), etc., to perform, when activated, one or more itscorresponding functions and may further include inferred coupling to oneor more other items. As may still further be used herein, the term“associated with”, includes direct and/or indirect coupling of separateitems and/or one item being embedded within another item.

As may be used herein, the term “compares favorably”, indicates that acomparison between two or more items, signals, etc., provides a desiredrelationship. For example, when the desired relationship is that signalA has a greater magnitude than signal B, a favorable comparison may beachieved when the magnitude of signal A is greater than that of signal Bor when the magnitude of signal B is less than that of signal A. As maybe used herein, the term “compares unfavorably”, indicates that acomparison between two or more items, signals, etc., fails to providethe desired relationship.

As may also be used herein, the terms “processing module”, “processingcircuit”, “processor”, and/or “processing unit” may be a singleprocessing device or a plurality of processing devices. Such aprocessing device may be a microprocessor, micro-controller, digitalsignal processor, microcomputer, central processing unit, fieldprogrammable gate array, programmable logic device, state machine, logiccircuitry, analog circuitry, digital circuitry, and/or any device thatmanipulates signals (analog and/or digital) based on hard coding of thecircuitry and/or operational instructions. The processing module,module, processing circuit, and/or processing unit may be, or furtherinclude, memory and/or an integrated memory element, which may be asingle memory device, a plurality of memory devices, and/or embeddedcircuitry of another processing module, module, processing circuit,and/or processing unit. Such a memory device may be a read-only memory,random access memory, volatile memory, non-volatile memory, staticmemory, dynamic memory, flash memory, cache memory, and/or any devicethat stores digital information. Note that if the processing module,module, processing circuit, and/or processing unit includes more thanone processing device, the processing devices may be centrally located(e.g., directly coupled together via a wired and/or wireless busstructure) or may be distributedly located (e.g., cloud computing viaindirect coupling via a local area network and/or a wide area network).Further note that if the processing module, module, processing circuit,and/or processing unit implements one or more of its functions via astate machine, analog circuitry, digital circuitry, and/or logiccircuitry, the memory and/or memory element storing the correspondingoperational instructions may be embedded within, or external to, thecircuitry comprising the state machine, analog circuitry, digitalcircuitry, and/or logic circuitry. Still further note that, the memoryelement may store, and the processing module, module, processingcircuit, and/or processing unit executes, hard coded and/or operationalinstructions corresponding to at least some of the steps and/orfunctions illustrated in one or more of the Figures. Such a memorydevice or memory element can be included in an article of manufacture.

One or more embodiments have been described above with the aid of methodsteps illustrating the performance of specified functions andrelationships thereof. The boundaries and sequence of these functionalbuilding blocks and method steps have been arbitrarily defined hereinfor convenience of description. Alternate boundaries and sequences canbe defined so long as the specified functions and relationships areappropriately performed. Any such alternate boundaries or sequences arethus within the scope and spirit of the claims. Further, the boundariesof these functional building blocks have been arbitrarily defined forconvenience of description. Alternate boundaries could be defined aslong as the certain significant functions are appropriately performed.Similarly, flow diagram blocks may also have been arbitrarily definedherein to illustrate certain significant functionality.

To the extent used, the flow diagram block boundaries and sequence couldhave been defined otherwise and still perform the certain significantfunctionality. Such alternate definitions of both functional buildingblocks and flow diagram blocks and sequences are thus within the scopeand spirit of the claims. One of average skill in the art will alsorecognize that the functional building blocks, and other illustrativeblocks, modules and components herein, can be implemented as illustratedor by discrete components, application specific integrated circuits,processors executing appropriate software and the like or anycombination thereof.

In addition, a flow diagram may include a “start” and/or “continue”indication. The “start” and “continue” indications reflect that thesteps presented can optionally be incorporated in or otherwise used inconjunction with other routines. In this context, “start” indicates thebeginning of the first step presented and may be preceded by otheractivities not specifically shown. Further, the “continue” indicationreflects that the steps presented may be performed multiple times and/ormay be succeeded by other activities not specifically shown. Further,while a flow diagram indicates a particular ordering of steps, otherorderings are likewise possible provided that the principles ofcausality are maintained.

The one or more embodiments are used herein to illustrate one or moreaspects, one or more features, one or more concepts, and/or one or moreexamples. A physical embodiment of an apparatus, an article ofmanufacture, a machine, and/or of a process may include one or more ofthe aspects, features, concepts, examples, etc. described with referenceto one or more of the embodiments discussed herein. Further, from Figureto Figure, the embodiments may incorporate the same or similarly namedfunctions, steps, modules, etc. that may use the same or differentreference numbers and, as such, the functions, steps, modules, etc. maybe the same or similar functions, steps, modules, etc. or differentones.

Unless specifically stated to the contra, signals to, from, and/orbetween elements in a figure of any of the figures presented herein maybe analog or digital, continuous time or discrete time, and single-endedor differential. For instance, if a signal path is shown as asingle-ended path, it also represents a differential signal path.Similarly, if a signal path is shown as a differential path, it alsorepresents a single-ended signal path. While one or more particulararchitectures are described herein, other architectures can likewise beimplemented that use one or more data buses not expressly shown, directconnectivity between elements, and/or indirect coupling between otherelements as recognized by one of average skill in the art.

The term “module” is used in the description of one or more of theembodiments. A module implements one or more functions via a device suchas a processor or other processing device or other hardware that mayinclude or operate in association with a memory that stores operationalinstructions. A module may operate independently and/or in conjunctionwith software and/or firmware. As also used herein, a module may containone or more sub-modules, each of which may be one or more modules.

As may further be used herein, a computer readable memory includes oneor more memory elements. A memory element may be a separate memorydevice, multiple memory devices, or a set of memory locations within amemory device. Such a memory device may be a read-only memory, randomaccess memory, volatile memory, non-volatile memory, static memory,dynamic memory, flash memory, cache memory, and/or any device thatstores digital information. The memory device may be in a form a solidstate memory, a hard drive memory, cloud memory, thumb drive, servermemory, computing device memory, and/or other physical medium forstoring digital information. A computer readable memory/storage medium,as used herein, is not to be construed as being transitory signals perse, such as radio waves or other freely propagating electromagneticwaves, electromagnetic waves propagating through a waveguide or othertransmission media (e.g., light pulses passing through a fiber-opticcable), or electrical signals transmitted through a wire.

While particular combinations of various functions and features of theone or more embodiments have been expressly described herein, othercombinations of these features and functions are likewise possible. Thepresent disclosure is not limited by the particular examples disclosedherein and expressly incorporates these other combinations.

What is claimed is:
 1. A method of storing data in a dispersed storagenetwork, the dispersed storage network including a plurality ofdispersed storage units, the method comprising: determining a minimumslice access rate for storing slices in a first memory of a firstdispersed storage unit of the plurality of dispersed storage units;determining a least access rate of a least accessed encoded data slicestored in the first memory of the first dispersed storage unit of theplurality of dispersed storage units; determining an estimated accessrate for an encoded data slice to be stored; determining whether tostore the encoded data slice to be stored in the first memory of thefirst dispersed storage unit of the plurality of dispersed storage unitsbased on the minimum slice access rate for storing slices in the firstmemory of the first dispersed storage unit of the plurality of dispersedstorage units, the least access rate of the least accessed encoded dataslice stored in the first memory of the first dispersed storage unit ofthe plurality of dispersed storage units and the estimated access ratefor the encoded data slice to be stored to produce a determination; andstoring the encoded data slice to be stored in the first memory based onthe determination.
 2. The method of claim 1, wherein first memoryincludes a small fast memory and wherein the first dispersed storageunit of the plurality of dispersed storage units further includes asecond memory, the second memory including a large slow memory.
 3. Themethod of claim 2 wherein the step of storing the encoded data slice tobe stored in the first memory based on the determination includestransferring the encoded data slice from the second memory to the firstmemory.
 4. The method of claim 1, wherein the step of determining theminimum slice access rate for storing slices in the first memory of thefirst dispersed storage unit of the plurality of dispersed storage unitsis based on one or more of a historical access rate, a memory wearfactor and a capacity level of the first memory.
 5. The method of claim4, wherein the memory wear factor includes a maximum number of writesper unit of time.
 6. The method of claim 1, wherein the step ofdetermining the least access rate of the least accessed encoded dataslice stored in the first memory of the first dispersed storage unit ofthe plurality of dispersed storage units includes one or more ofmeasuring access rates of encoded data slices stored in the first memoryand identifying a minimum access rate.
 7. The method of claim 1, whereinthe step of determining the estimated access rate for the encoded dataslice to be stored includes one or more of identifying the encoded dataslice to be stored, measuring an actual access rate and receiving theestimated access rate.
 8. The method of claim 1 wherein the step ofdetermining whether to store the encoded data slice to be stored in thefirst memory of the first dispersed storage unit of the plurality ofdispersed storage units includes indicating to store the encoded dataslice to be stored in the first memory when the estimated access rate isgreater than the minimum slice access rate for storing slices in thefirst memory of the first dispersed storage unit of the plurality ofdispersed storage units and the estimated access rate is greater thanthe least access rate of the least accessed encoded data slice stored inthe first memory of the first dispersed storage unit of the plurality ofdispersed storage units.
 9. A first dispersed storage unit for use in adispersed storage network, the dispersed storage network including aplurality of dispersed storage units, the first dispersed storage unitcomprising: a communications interface; a first memory; a second memory;a computer processor; where the second memory includes instructions forcausing the computer processor to: determine a minimum slice access ratefor storing slices in the first memory of the first dispersed storageunit of the plurality of dispersed storage units; determine a leastaccess rate of a least accessed encoded data slice stored in the firstmemory of the first dispersed storage unit of the plurality of dispersedstorage units; determine an estimated access rate for an encoded dataslice to be stored; determine whether to store the encoded data slice tobe stored in the first memory of the first dispersed storage unit of theplurality of dispersed storage units based on the minimum slice accessrate for storing slices in the first memory of the first dispersedstorage unit of the plurality of dispersed storage units, the leastaccess rate of the least accessed encoded data slice stored in the firstmemory of the first dispersed storage unit of the plurality of dispersedstorage units and the estimated access rate for the encoded data sliceto be stored to produce a determination; and store the encoded dataslice to be stored in the first memory based on the determination. 10.The first dispersed storage unit of claim 9, wherein first memoryincludes a small fast memory and wherein the second memory includes alarge slow memory.
 11. The first dispersed storage unit of claim 10,wherein the second memory includes instructions for further causing thecomputer processor to transfer the encoded data slice from the secondmemory to the first memory.
 12. The first dispersed storage unit ofclaim 9, wherein the instructions for causing the computer processor todetermine the minimum slice access rate for storing slices in the firstmemory of the first dispersed storage unit of the plurality of dispersedstorage units are based on one or more of a historical access rate, amemory wear factor and a capacity level of the first memory.
 13. Thefirst dispersed storage unit of claim 12, wherein the memory wear factorincludes a maximum number of writes per unit of time.
 14. The firstdispersed storage unit of claim 9, wherein the second memory includesinstructions for further causing the computer processor to, one or moreof, measure access rates of encoded data slices stored in the firstmemory and identify a minimum access rate.
 15. The first dispersedstorage unit of claim 9, wherein the second memory includes instructionsfor further causing the computer processor to, one or more, of identifythe encoded data slice to be stored, measure an actual access rate andreceive the estimated access rate.
 16. The first dispersed storage unitof claim 9, wherein the second memory includes instructions for furthercausing the computer processor to indicate to store the encoded dataslice to be stored in the first memory when the estimated access rate isgreater than the minimum slice access rate for storing slices in thefirst memory of the first dispersed storage unit of the plurality ofdispersed storage units and the estimated access rate is greater thanthe least access rate of the least accessed encoded data slice stored inthe first memory of the first dispersed storage unit of the plurality ofdispersed storage units.
 17. A dispersed storage network comprising: aplurality of dispersed storage units; wherein a first dispersed storageunit of the plurality of dispersed storage units includes: acommunications interface; a first memory; a second memory; a computerprocessor; where the second memory includes instructions for causing thecomputer processor to: determine a minimum slice access rate for storingslices in the first memory of the first dispersed storage unit of theplurality of dispersed storage units; determine a least access rate of aleast accessed encoded data slice stored in the first memory of thefirst dispersed storage unit of the plurality of dispersed storageunits; determine an estimated access rate for an encoded data slice tobe stored; determine whether to store the encoded data slice to bestored in the first memory of the first dispersed storage unit of theplurality of dispersed storage units based on the minimum slice accessrate for storing slices in the first memory of the first dispersedstorage unit of the plurality of dispersed storage units, the leastaccess rate of the least accessed encoded data slice stored in the firstmemory of the first dispersed storage unit of the plurality of dispersedstorage units and the estimated access rate for the encoded data sliceto be stored to produce a determination; and store the encoded dataslice to be stored in the first memory based on the determination. 18.The dispersed storage network of claim 17, wherein first memory includesa small fast memory and the second memory includes a large slow memory.19. The dispersed storage network of claim 18, wherein the second memoryincludes instructions for further causing the computer processor totransfer the encoded data slice from the second memory to the firstmemory.
 20. The dispersed storage network of claim 17, wherein theinstructions for causing the computer processor to determine the minimumslice access rate for storing slices in the first memory of the firstdispersed storage unit of the plurality of dispersed storage units arebased on one or more of a historical access rate, a memory wear factorand a capacity level of the first memory.